Generally, in integrated circuits, a soft-fail (or soft-failure) may be described as a minor defect in an electrical connection. The defect in the electrical connection may lead to an increase in electrical resistance through the electrical connection. Typically, the defect may result in an increase in the electrical resistance on the order of a few times to several thousand times the electrical resistance of a defect-free electrical connection.
The increase in the electrical resistance of the electrical connection may introduce additional delay to a signal propagation path containing the electrical connection. FIG. 1a illustrates two electrical signal paths, a first path 105 labeled “NORMAL” and a second path 110 labeled “HI-R.” Signal path 105 includes through-silicon via (TSV) 106, and signal path 110 includes TSV 112. TSV 106 is a normal TSV with the resistance within design specification. The faulty TSV 112, which may include a micro void, has an electrical resistance higher than what design specification allows.
FIG. 1b illustrates three signal traces, a first trace 155 representing an input signal, a second trace 160 representing an electrical signal measured at an output of first path 105, and a third trace 165 representing an electrical signal measured at an output of second path 110. Both electrical signal paths shown in FIG. 1 are connected to the input signal labeled “IN.” Both second trace 160 and third trace 165 arise from the input signal (first trace 155) that transition from a low electric potential to a high electric potential.
Due to an inherent electrical resistance of vias, an electrical signal propagating through first path 105 will experience a small propagation delay. However, the propagation delay is negligible. A rise time of the input signal propagating through first path 105 (shown as interval 175) may be substantially equal to a rise time of the input signal (shown as interval 170).
However, due to a significant increase in electrical resistance of second path 110, a rise time of the input signal propagating through second path 110 (shown as interval 180) may be substantially greater than a rise time of the input signal (shown as interval 170). Duration of interval 180 may be a function of the increase in electrical resistance due to the faulty via, with a greater increase in electrical resistance resulting in a greater duration of interval 180.
The increase in propagation delay due to a soft-fail may be detected directly by measuring the resistance of TSVs 106 and 112 shown in FIG. 1 by applying signal 155 to the input of each of the signal paths such as 105 and 112, and measuring the output signal. This method, however, suffers from the throughput problem since the detection has to be performed for each of the signal paths.
An alternative method for detecting likely fault in TSVs is to connect the TSVs as a daisy chain, and input a signal into the input of the daisy chain, and detect the output signal at the output of the daisy chain. Although the throughput may be improved by using this method, the accuracy of this method is degraded. For example, if one of the TSVs in the daisy chain has a soft-failure, and its resistance increases by tens of times, since the increase in the faulty TSV is averaged to a large number of TSVs, which may include hundreds of TSVs, the overall increase in the resistance of the entire daisy chain (and the resulting detected propagation delay of the daisy chain) may still be within the standard manufacturing tolerance, and may be acceptable. Accordingly, the soft-failure in the TSV may not be detectable.